<p><span style="font-size: 12pt"><span>At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.</span></span></p> <p><span style="font-size: 12pt"><span><br>Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. </span><span>Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions. </span><br></span></p> <p><span style="font-size: 12pt"><span> </span></span></p> <p><span style="font-size: 12pt"><span>We are a fast-growing, forward-thinking team of </span><span>architects, engineers, and business professionals with a proven track record of building successful products and companies. </span><span>As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles</span><span>. </span><span> </span></span></p> <p><span style="font-size: 12pt"> </span></p> <p><span style="font-size: 12pt">Cornelis Networks is hiring Mid-Level and Senior ASIC Verification Engineers with advanced skills and knowledge in key areas required to verify world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions.</span></p> <p><span style="font-size: 12pt"> </span></p> <p><span style="font-size: 12pt; font-weight: bold">Key Responsibilities:</span></p> <ul> <li><span style="font-size: 12pt">Participate in development of UVM environments to verify RTL at block, unit, and SoC levels</span></li> <li><span style="font-size: 12pt">Write and execute tests according to verification plans</span></li> <li><span style="font-size: 12pt">Instrument TB for functional and code coverage; collect and analyze coverage results</span></li> <li><span style="font-size: 12pt">Execute formal verification of block level RTL</span></li> <li><span style="font-size: 12pt">Participate in post-silicon verification</span><br><br></li> </ul> <p><span style="font-size: 12pt; font-weight: bold">Preferred Qualifications:</span></p> <ul> <li><span style="font-size: 12pt">M.S. Degree in Computer Engineering, Computer Science, or Electrical Engineering</span></li> <li><span style="font-size: 12pt">Track record of first-pass success in ASIC and Systems</span><br><br></li> </ul> <p><span style="font-size: 12pt; font-weight: bold">Minimum Qualifications:</span></p> <ul> <li><span style="font-size: 12pt">Must be able to read, write and speak English at a level of professional working proficiency.</span></li> <li><span style="font-size: 12pt">3 + years' post-college experience in verification</span></li> <li><span style="font-size: 12pt">3 + years' post-college experience in one or more scripting languages (TCL, Python, Perl, Shell-scripting)</span></li> <li><span style="font-size: 12pt">3 + years' post-college experience validating complex SoCs that include multiple clock and reset domains</span></li> <li><span>Experience in <span style="font-weight: bold">UVM based</span> test bench development</span></li> <li><span style="font-size: 12pt">B.S. Degree in Computer Engineering, Computer Science, or Electrical Engineering</span></li> </ul> <p><span style="font-size: 12pt"> </span></p> <p><span style="font-size: 12pt"><span style="font-weight: bold">Job Location:<span> </span></span>This role may work remote from Costa Rica via an EOR (Employer of Record).</span></p> <p><br></p> <p><span style="font-size: 12pt"><span>At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.</span><span> </span></span></p> <p><br></p> <p><span style="font-size: 12pt"><span>Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. </span><span>We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span><span> </span></span></p><br><hr><div class="fabric-5qovnk-root MuiBox-root css-witlqh" data-fabric-component="Flex"><div class="fabric-5qovnk-root MuiBox-root css-1phs5iq" data-fabric-component="Flex"><div class="fabric-2lfz5e-root MuiBox-root css-jipda8" data-fabric-component="LayoutBox"><p class="fabric-v3bc9l-root" data-fabric-component="BodyText">Location</p></div><div class="fabric-15808a6-root MuiBox-root css-4cxybv" data-fabric-component="LayoutBox"><p class="fabric-958q8r-root" data-fabric-component="BodyText">San Jose, San Jose Province (Remote)</p></div><hr class="MuiDivider-root fabric-jcid1o-root MuiDivider-fullWidth MuiBox-root css-40h3v3" data-fabric-component="Divider"></div><div class="fabric-5qovnk-root MuiBox-root css-1phs5iq" data-fabric-component="Flex"><div class="fabric-2lfz5e-root MuiBox-root css-jipda8" data-fabric-component="LayoutBox"><p class="fabric-v3bc9l-root" data-fabric-component="BodyText">Department</p></div><div class="fabric-15808a6-root MuiBox-root css-4cxybv" data-fabric-component="LayoutBox"><p class="fabric-958q8r-root" data-fabric-component="BodyText">ASIC Engineering</p></div><hr class="MuiDivider-root fabric-jcid1o-root MuiDivider-fullWidth MuiBox-root css-40h3v3" data-fabric-component="Divider"></div><div class="fabric-5qovnk-root MuiBox-root css-1phs5iq" data-fabric-component="Flex"><div class="fabric-2lfz5e-root MuiBox-root css-jipda8" data-fabric-component="LayoutBox"><p class="fabric-v3bc9l-root" data-fabric-component="BodyText">Employment Type</p></div><div class="fabric-15808a6-root MuiBox-root css-4cxybv" data-fabric-component="LayoutBox"><p class="fabric-958q8r-root" data-fabric-component="BodyText">Full-Time</p></div><hr class="MuiDivider-root fabric-jcid1o-root MuiDivider-fullWidth MuiBox-root css-40h3v3" data-fabric-component="Divider"></div></div>